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Patent Examiner Woo Kyung Lee

Art Unit 2815 · Semiconductor Transistors, Memory, LEDs & Packaging · Tech Center 2800 · 271 applications filed 2021–2026

Average · easier than 55% of examiners● Free examiner data

Woo Kyung Lee is a USPTO patent examiner in Art Unit 2815 (Semiconductor Transistors, Memory, LEDs & Packaging) with 271 applications from filing years 2021–2026. Examiner Lee's allowance rate is 86.2%, above the 82.4% USPTO average for applications filed in the same years. The examiner ranks easier than 55% of examiners. In 2021, decided applications with an examiner interview were allowed 41.3 percentage points more often than those without.

Draft a response to Examiner LeeSee the strategy data ↓

Data through October 2026 from USPTO Patent Center (formerly PAIR) · Methodology

Overview

Free
Difficulty · Average
easier than 55% of examiners
Easier44th percentileHarder
Allowance rate vs peers
Examiner Lee86.2%
Art Unit 281587.4%
USPTO average82.4%
Allowance rate
86.2%
▲ USPTO avg 82.4%
Applications
271
filing years 2021–2026
First-action allowance
8.3%
patented with no rejection
Abandoned
9.2%
share of applications
Avg office actions
1.8
USPTO avg 1.3
Days to first OA
836
▲ USPTO 632
RCE rate
37.3%
USPTO 19.4%
Interview rate
37.3%
USPTO 27.4%

Examiner details

  • Art unit2815 · Semiconductor Transistors, Memory, LEDs & Packaging
  • Title / gradePatent Examiner · GS-12
  • Service4 years
  • PhoneOn each office action
  • In USPTO recordsLEE, WOO KYUNG
Work reviewed by a primary examiner

Office actions from Examiner Lee are reviewed and signed by a more senior examiner before issuing, so clear written arguments carry extra weight.

Examines (USPC classes)
257 · Active Solid-State Devices (Transistors, Diodes)438 · Semiconductor Device Manufacturing: Process

How to improve your odds with Examiner Lee

  • The data favors an interview. Interviewed cases were allowed more often in all 3 measured years, by 6.9 to 41.3 points.
  • Plan for the timeline. First office action averages 836 days vs the 632-day USPTO norm.
  • Expect a §103. Obviousness is the most-issued rejection (249), and applicants overcame it 63.8% of the time.
  • The data favors an RCE here. Cases with an RCE were allowed more often in all 3 measured years, by 5.6 to 39.3 points.

Historical patterns from this examiner's past cases, shown for general information. This is not legal advice and does not predict the outcome of any specific application. Decisions about interviews, RCEs, and claim strategy should be made with a licensed patent attorney or agent.

Rejection patterns & how they get overcome

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§102 Novelty140 issued · 78.4% overcome
§103 Obviousness249 issued · 63.8% overcome
§112 Definiteness & disclosure164 issued · 69.3% overcome
How applicants traverse §103 rejections🔒 Members

Of the 60 winning responses to Examiner Lee's §103 rejections that Boundly has classified, 55 (92%) amended the claims and argued, 3 argued without amending, and 2 amended without arguing. Each winning response, with its arguments and claim amendments, is in the file wrapper.

Read the winning §103 argumentsFull REMARKS, amendments, claim trees & redlines from the file wrappers
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Draft your response with Examiner Lee's record and Art Unit 2815's history in view, including the rejection patterns, the interview record, and the arguments that have overcome them. See office action responses in AI Studio.

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RCE behavior

Allowance after a Request for Continued Examination versus without one, per year. Use it to judge whether an RCE is worth the cost in front of Examiner Lee.

YearRCE rateAllowance w/ RCEAllowance w/oDelta
202320.0%100.0%94.4%+5.6pp
202251.4%100.0%75.0%+25.0pp
202170.0%91.7%52.4%+39.3pp

Recent outcomes

Free🔒 Case detail for members
App #TitleOutcomeOAsArguments & redline
18/240041Non-Volatile Memory DevicePatented1🔒 View
18/217701Semiconductor Package and Method for Fabricating the SamePatented1🔒 View
18/424791Gate Sidewall Structures of Semiconductor Devices and Methods of Forming the SamePatented0🔒 View
18/419385Fabrication Method for a Three-Dimensional Memory Array of Thin-Film Ferroelectric Transistors Using High-Aspect-Ratio Local Word Line Damascene ProcessPatented0🔒 View
See all 271 applications with full file-wrapper detailOffice action text, attorney arguments, amendments & claim-by-claim track changes
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Art Unit 2815 technology

Transistor structuresMemory & capacitorsLight-emitting diodesSemiconductor packagingTop CPC H10D · H10W · H10H
About this examiner. Woo Kyung Lee examines in Art Unit 2815 (Semiconductor Transistors, Memory, LEDs & Packaging, Tech Center 2800). The art unit's docket includes transistor structures, memory & capacitors, light-emitting diodes, and semiconductor packaging.

Frequently asked questions

What is Examiner Woo Kyung Lee's allowance rate?
Examiner Lee's allowance rate is 86.2%, compared with 82.4% across the USPTO and 87.4% in Art Unit 2815 for applications filed in the same years. That rate ranks Examiner Lee easier than 55% of examiners.
Is Examiner Lee a hard examiner?
Not especially. Examiner Lee ranks easier than 55% of examiners, in the 44th difficulty percentile (average). Examiner Lee has an 86.2% allowance rate versus 82.4% across the USPTO and 87.4% in Art Unit 2815, 1.8 office actions per application versus 1.3, and an RCE rate of 37.3% versus 19.4% across the USPTO, for applications filed in the same years.
Do examiner interviews help with Examiner Lee?
In this examiner's record, yes. Decided applications with an interview were allowed more often in each of the 3 measured years, by 6.9 to 41.3 percentage points. In 2021, 93.5% of decided applications with an interview were allowed, versus 52.2% of those without.
What is Examiner Lee's most common rejection?
§103 obviousness, issued 249 times in the data. Applicants overcame it 63.8% of the time. Of the 60 winning responses Boundly has classified, 55 amended the claims and argued.
Is an RCE worth filing with Examiner Lee?
In this examiner's record, yes. Decided applications with an RCE were allowed more often in each of the 3 measured years, by 5.6 to 39.3 percentage points. In 2021, 91.7% of decided applications with an RCE were allowed, versus 52.4% of those without one.
How long until the first office action from Examiner Lee?
About 836 days on average, versus 632 days across the USPTO for applications filed in the same years.

Put Examiner Lee's data to work on your next response.

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Statistics are computed by Boundly Prosecution Intel from USPTO Patent Center (formerly PAIR) file wrappers for filing years 2021–2026, refreshed regularly. Allowance rate (sometimes called grant rate) is the share of disposed applications that issued as patents. Office actions here are non-final and final rejections, so restriction requirements and allowances are not counted. USPTO benchmarks are weighted to each examiner's mix of filing years, and art-unit benchmarks to the art units and filing years of the examiner's own applications, so they compare like for like. The difficulty percentile ranks examiners, each counted once, so it can point the other way from the USPTO average, which counts applications. See how each number is computed. The year-by-year interview and RCE tables show up to four recent filing years, leaving out the newest one and any year with fewer than ten applications or five decided applications on either side. Historical data is provided for informational purposes only. Past examiner behavior does not guarantee future outcomes, and nothing here is legal advice or a substitute for advice from a licensed patent attorney or agent. Are you Woo Kyung Lee, or see an error? Request a correction.